Organic Interposers Using Zero-Misalignment-Via Technology and Silicon Wafer Carriers for Large Area Wafer-Level Package Applications

• Published in: 2024 IEEE 74th Electronic Components and Technology Conference (ECTC) pp. 842 - 848
• Main Authors: Aleksov, Aleksandar, Talukdar, Tushar, Strong, Veronica, Sounart, Thomas, Sawyer, Holly, Aubertine, Carolyn, Swan, Johanna
• Format: Conference Proceeding
• Language: English
• Published: IEEE 28.05.2024
• Subjects: Electronic components; Electronic packaging thermal management; Finite element analysis; Glass; interposer; Lithography; organic; redistribution layer; self-aligned; Silicon; Thermal expansion; via; wafer-level-packaging
• ISSN: 2377-5726
• DOI: 10.1109/ECTC51529.2024.00135

In this paper we demonstrate a novel approach to creating large area organic interposers with high-density interconnects for a die-last interposer flow. We manufactured a 2layer redistribution-layer (RDL) unit of ~ 2070mm 2 area using the Zero-Misalignment-Via technology (ZMV). ZMV is a self-aligned via process that is tailored for delivering self-aligned vias in a semi-additive process flow. We manufactured the interconnect layers using an organic-based spin-coated dielectric material that has a low coefficient of thermal expansion (CTE) of ~ 19 ppm/°C, close to the CTE of Copper (16-17 ppm/°C). The low CTE of the material significantly decreases via stress during thermal cycling, a feature captured by finite-element modeling (FEM). While ZMV is not limited to two interconnect layers, a 2-layer short-loop stack was chosen as the simplest case to demonstrate all necessary building blocks for the ZMV technology, as well as to integrate design elements known from package-substrates into RDLs. One of the interconnect layers had high density interconnects with a line-density of 333 traces/mm, limited by the lithography tool used. The other layer consisted of large Cu-planes that in an electrically active system would be used for ground referencing and/or power delivery. Such planes are typical for package substrates but are a new design element integrated into the presented RDL layer stack. The ~3 reticle sized unit was manufactured using reticle stitching, demonstrating that the ZMV process is fully compatible with this process and hence can be used to manufacture wafer-sized interposers for future high-performance compute (HPC) applications if so required. This ZMV-based organic interposer technology is fully compatible with Silicon carrier wafers, by utilizing a novel IR debond method negating the necessity for glass carrier wafers, allowing for full compatibility with an existing silicon-centric toolset.