A 0.297-pJ/bit 50.4-Gb/s/wire Inverter-Based Short-Reach Simultaneous Bidirectional Transceiver for Die-to-Die Interface in 5nm CMOS

This paper presents a clock-forwarded, Inverter-based Short-Reach Simultaneous Bi-Directional (ISR-SBD) PHY targeted for die-to-die communication over silicon interposer or similar high-density interconnect. Fabricated in a 5nm standard CMOS process, ISR-SBD PHY demonstrates 50.4Gb/s/wire (25.2Gb/s...

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Bibliographic Details
Published in2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) pp. 154 - 155
Main Authors Nishi, Yoshinori, Poulton, John W., Chen, Xi, Song, Sanquan, Zimmer, Brian, Turner, Walker J., Tell, Stephen G., Nedovic, Nikola, Wilson, John M., Dally, William J., Gray, C. Thomas
Format Conference Proceeding
LanguageEnglish
Published IEEE 12.06.2022
Subjects
Bidirectional control
chip-to-chip and interposer
CMOS process
CoWoS
die-to-die
InFO
Integrated circuit interconnections
ISR
SBD
Silicon
simultaneous bidirectional
System-on-chip
Transceivers
Very large scale integration
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Summary:This paper presents a clock-forwarded, Inverter-based Short-Reach Simultaneous Bi-Directional (ISR-SBD) PHY targeted for die-to-die communication over silicon interposer or similar high-density interconnect. Fabricated in a 5nm standard CMOS process, ISR-SBD PHY demonstrates 50.4Gb/s/wire (25.2Gb/s each direction) and 0.297pJ/bit on a 0.75V supply over a 1.2mm on-chip channel.
ISSN:2158-9682
DOI:10.1109/VLSITechnologyandCir46769.2022.9830174