TCAD Framework for HCD Kinetics in Low VD Devices Spanning Full VG/VD Space

• Published in: IEEE transactions on electron devices Vol. 67; no. 11; pp. 4749 - 4756
• Main Authors: Sharma, Uma, Duan, Meng, Diwakar, Himanshu, Thakor, Karansingh, Wong, Hiu Yung, Motzny, Steve, Dolgos, Denis, Mahapatra, Souvik
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.11.2020; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Drift; Hot carriers; interface trap generation; Kinetic theory; Kinetics; Logic gates; MOSFETs; Negative bias temperature instability; parametric drift; reaction diffusion drift (RDD) model; self-heating (SH) effect; Solid modeling; Stress; technology CAD (TCAD); Thermal variables control
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2020.3021360

The time kinetics of hot carrier degradation (HCD) is modeled using a reaction diffusion drift (RDD) framework. It is incorporated into Sentaurus Device TCAD and validated using conduction mode HCD data in n- and p-channel MOSFETs and FinFETs. RDD-enabled TCAD calculates carrier-energy-initiated generation of interface traps (<inline-formula> <tex-math notation="LaTeX">\Delta {N}_{\text {IT}} </tex-math></inline-formula>) and the impact of the resulting localized charges on device parametric drift. HCD at various gate (<inline-formula> <tex-math notation="LaTeX">{V}_{\text {G}} </tex-math></inline-formula>) and drain (<inline-formula> <tex-math notation="LaTeX">{V}_{\text {D}} </tex-math></inline-formula>) biases spanning various modes (<inline-formula> <tex-math notation="LaTeX">{V}_{\text {G}}\le </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">>{V}_{\text {D}} </tex-math></inline-formula>) are simulated for low stress <inline-formula> <tex-math notation="LaTeX">{V}_{\text {D}} </tex-math></inline-formula> (< 3 V). The self-heating (SH)-effect-induced temperature (<inline-formula> <tex-math notation="LaTeX">\textit {T} </tex-math></inline-formula>) increase is invoked for FinFETs. Data from various experiments are analyzed and a wide range of power-law time kinetics slope (<inline-formula> <tex-math notation="LaTeX">{n} </tex-math></inline-formula>) is explained.