FPGA Implementation of I2C Based Networking System for Secure Data Transmission

In this paper, the main focus was to implement the I 2 C (Inter Integrated Circuit) bus on Altera DE2-115 development board. I 2 C bus design is modeled using VHDL and synthesised using Quartus II. In this work, an attempt to simulate the I 2 C write and read operation using ModelSim is made. Theref...

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Bibliographic Details
Published in2019 International Conference on Advances in Computing, Communication and Control (ICAC3) pp. 1 - 5
Main Authors Katkar, Vrushali S., Shah, Divya K., Ashtekar, Shweta S.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.12.2019
Subjects
Clocks
Field programmable gate arrays
FPGA
Hardware
Hardware Resource Utilization
I2C
Master
ModelSim Simulation
Phase locked loops
Protocols
Resource management
Slave
VHDL
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DOI10.1109/ICAC347590.2019.9036785

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Summary:In this paper, the main focus was to implement the I 2 C (Inter Integrated Circuit) bus on Altera DE2-115 development board. I 2 C bus design is modeled using VHDL and synthesised using Quartus II. In this work, an attempt to simulate the I 2 C write and read operation using ModelSim is made. Therefore implement I 2 C bus on Field Programmable Gate Arrays(FPGA)gives greater straightforwardness since it requires just two-wires and less number of association pins. FPGA provides multiple IO interfaces as compared other hard core. The sole reason to use I 2 C instead of other protocol is because of its two wire data transfer and security. This work also presents the number of Logic Elements, Logic registers, Pins, Memory Bits, Embedded Multiplier, and PLLs used in the design.
DOI:10.1109/ICAC347590.2019.9036785