A Heterogeneous HEVC Video Encoder System Based on Two-Level CPU-FPGA Computing Architecture

• Published in: 2021 IEEE 14th International Conference on ASIC (ASICON) pp. 1 - 4
• Main Authors: Qiu, Yudi, Jiao, Jie, Tang, Yuxin, Liu, Yanwei, Ren, Jianyu, Zeng, Xiaoyang, Fan, Yibo
• Format: Conference Proceeding
• Language: English
• Published: IEEE 26.10.2021
• Subjects: Encoding; Hardware acceleration; Quality assessment; Real-time systems; Servers; Software; Streaming media

To trade off the speed and quality of video encoding, the heterogeneous methods to compress video have become a research hotspot. This paper proposes a CPU-FPGA HEVC video encoder system based on OpenPOWER platform. For software, x265 is optimized by instruction replacement and binding, which achiev...