A Heterogeneous HEVC Video Encoder System Based on Two-Level CPU-FPGA Computing Architecture

To trade off the speed and quality of video encoding, the heterogeneous methods to compress video have become a research hotspot. This paper proposes a CPU-FPGA HEVC video encoder system based on OpenPOWER platform. For software, x265 is optimized by instruction replacement and binding, which achiev...

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Bibliographic Details
Published in2021 IEEE 14th International Conference on ASIC (ASICON) pp. 1 - 4
Main Authors Qiu, Yudi, Jiao, Jie, Tang, Yuxin, Liu, Yanwei, Ren, Jianyu, Zeng, Xiaoyang, Fan, Yibo
Format Conference Proceeding
LanguageEnglish
Published IEEE 26.10.2021
Subjects
Encoding
Hardware acceleration
Quality assessment
Real-time systems
Servers
Software
Streaming media
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Summary:To trade off the speed and quality of video encoding, the heterogeneous methods to compress video have become a research hotspot. This paper proposes a CPU-FPGA HEVC video encoder system based on OpenPOWER platform. For software, x265 is optimized by instruction replacement and binding, which achieves 24.5% average encoding performance improvement. For hardware, some functions of x265 are implemented as hardware accelerators in two levels. Frame-level acceleration implements the whole inter encoder on two FPGAs and supports 4K@75fps real-time video encoding. For functional-unit-level acceleration, some sub-functions of x265, such as 32×32 blocks of inverse discrete cosine transform (IDCT) and fractional motion estimation (FME), are implemented to achieve encoding performance improvement without video quality loss.
ISSN:2162-755X
DOI:10.1109/ASICON52560.2021.9620382