Performance Evaluation of Multilevel Coded FEC with Register-Transfer-Level Emulation

We demonstrated hardware emulations to evaluate the error-correction performance for a FEC scheme with multilevel coding. It has enabled the measurement of BER to reach the order of 10 −14 for the decoded signal.

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Bibliographic Details
Published in2022 27th OptoElectronics and Communications Conference (OECC) and 2022 International Conference on Photonics in Switching and Computing (PSC) pp. 1 - 3
Main Authors Konno, Toshihiro, Mikami, Kazumasa, Sugiyama, Junichi, Koganei, Yohei
Format Conference Proceeding
LanguageEnglish
Published IEICE 03.07.2022
Subjects
Emulation
Encoding
Forward error correction
Hardware
Hardware emulation
Multilevel coding
Parity check codes
Performance evaluation
Register-transfer-level
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Summary:We demonstrated hardware emulations to evaluate the error-correction performance for a FEC scheme with multilevel coding. It has enabled the measurement of BER to reach the order of 10 −14 for the decoded signal.
DOI:10.23919/OECC/PSC53152.2022.9849856