STI Gap-Fill Technology and Flowable CVD Process Application

With CMOS device feature size down-scaling, semiconductor manufacture industry encounters many new challenges. From 40 nm CMOS technology nodes, especially for 28nm and beyond, STI structure become more challenging due to shrinking geometries and stricter device leakage requirements. The size of mic...

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Bibliographic Details
Published in2021 China Semiconductor Technology International Conference (CSTIC) pp. 1 - 2
Main Authors Sun, Yan, Wei, SiMeng
Format Conference Proceeding
LanguageEnglish
Published IEEE 14.03.2021
Subjects
Annealing
CMOS technology
Filling
Furnaces
Geometry
Industries
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Summary:With CMOS device feature size down-scaling, semiconductor manufacture industry encounters many new challenges. From 40 nm CMOS technology nodes, especially for 28nm and beyond, STI structure become more challenging due to shrinking geometries and stricter device leakage requirements. The size of micro-shrinkage in the horizontal direction larger than vertical direction, which lead to the increase of the aspect ratio of the grooves. As for gas-fill materials, from HDP, HARP, SOD(Spin-on Dielectric), to flowable chemical vapor deposition (FCVD), stronger ability is requested in filling higher aspect ratio gap of vertical trench, through optimizing the annealing conditions, the as-obtained film can satisfy the STI requirements finally. This paper focus on the context of gap fill technology, especially advanced FCVD and subsequent anneal process which could be implemented by furnace tools with new challenges.
DOI:10.1109/CSTIC52283.2021.9461477