A low noise fully-integrated readout electronic with pile-up rejector for particle detector

• Published in: Proceedings (International Conference on ASIC) pp. 1 - 4
• Main Authors: Ma, Kangwei, Zhou, Fei, Zhang, Yacong, Lu, Wengao, Chen, Zhongjian
• Format: Conference Proceeding
• Language: English
• Published: IEEE 26.10.2021
• Subjects: Capacitance; Conferences; Detectors; Radiation detectors; Readout electronics; Registers; Silicon
• ISSN: 2162-755X
• DOI: 10.1109/ASICON52560.2021.9620413

A low noise readout electronic with high counting rate for radiation particle silicon detectors is presented. The system is fully integrated except for the particle detectors. It consists of a low noise front-end circuit for processing the detector signal of charge pulse and a high-performance successive approximation register A/D converter. A control logic with pile-up rejector is used to ensure the validity of the digital output data and the correct handshaking between the front-end and ADC. The design of early reset and baseline voltage discrimination is adopted to reject pile-up. The chip is designed and simulated in 180nm process. Finally, the chip achieves an equivalent noise charge (ENC) 871 e - with the detector capacitance 20 pF and pulse duration 500ns. The linear gain of 52.1 mV/fC and 16.7 mV/fC with the input charge range 6 Ke - ~406 Ke - .