The 24\times 24 Reversible Vedic Multiplier

Multipliers are one of the fundamental components of computational units in processors. The need of the hour is to increase the speed of computing units which in turn improves the speed and performance of processors. One such approach is the Vedic multiplier, which is capable of performing faster mu...

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Bibliographic Details
Published in2021 IEEE Mysore Sub Section International Conference (MysuruCon) pp. 378 - 385
Main Authors D, Krishnaveni, K, Supriya, H R, Suhas, N, Varshini, R, Sushma, M, Geetha Priya
Format Conference Proceeding
LanguageEnglish
Published IEEE 24.10.2021
Subjects
Constant inputs
Costs
Garbage outputs
IEEE Sections
Logic gates
Multiplier
Optical computing
Optical losses
Program processors
Quantum computing
Quantum cost
Reversible gates
Urdhva-Tiryagbhyam
Vedic multiplier
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Summary:Multipliers are one of the fundamental components of computational units in processors. The need of the hour is to increase the speed of computing units which in turn improves the speed and performance of processors. One such approach is the Vedic multiplier, which is capable of performing faster multiplications. Reversible logic is the field that has the potential to decrease power losses and is used in the field of low power CMOS design, optical computing, nanotechnology and quantum computing. The 24x24 Reversible Vedic multiplier using U rdhva- Tiryagbhyam sutra is proposed in this paper. With the help of Xilinx tools, the proposed multiplier is designed, synthesized, and tested. This design increases the speed of computation with reduced power dissipation. Thus, 24x24 reversible Vedic multiplier acts as primary block for most of low power arithmetic computations.
DOI:10.1109/MysuruCon52639.2021.9641598