A −68 dB THD, 0.6 mm2 Active Area Biosignal Acquisition System With a 40-320 Hz Duty-Cycle Controlled Filter
This paper presents a reconfigurable front-end (FE) circuit for acquiring various low-frequency biomedical signals. An energy and area-efficient tunable filter is proposed for adapting the FE bandwidth to the signal of interest. The filter is designed using a switched-R-MOSFET-C (SRMC) technique to...
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Published in | IEEE transactions on circuits and systems. I, Regular papers Vol. 67; no. 1; pp. 48 - 59 |
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Main Authors | , , |
Format | Journal Article |
Language | English |
Published |
New York
IEEE
01.01.2020
The Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Subjects | |
Online Access | Get full text |
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Summary: | This paper presents a reconfigurable front-end (FE) circuit for acquiring various low-frequency biomedical signals. An energy and area-efficient tunable filter is proposed for adapting the FE bandwidth to the signal of interest. The filter is designed using a switched-R-MOSFET-C (SRMC) technique to realize the needed ultra-low cutoff frequency. An 8-bit SAR ADC, following the filter, quantizes the signal, while the SAR control logic is re-used to accurately program the filter bandwidth from 40 Hz to 320 Hz with a 40 Hz step. The prototype chip includes the complete FE system, formed of an instrumentation amplifier (IA), a programmable-gain amplifier (PGA), and the proposed tunable filter followed by the SAR ADC. Implemented in 0.13 μm CMOS technology, the IC occupies a 0.6 mm2 active area while consuming 6.3 μW dc power from a 2-V supply. Measurement results show a FE gain range of 43-55 dB with an integrated input-referred noise (V IRN ) of 3.45 μV rms , a 66 dB dynamic range (DR), and a total-harmonic distortion (THD) of -68 dB at an input amplitude of 6 mVPP. The effective number of bits (ENOB) for the ADC is 7.921 bits at 1-kS/s. In real-time Electrocardiogram (ECG), Electromyography (EMG), and Electroencephalography (EEG) measurements, high-fidelity waveforms are acquired using the proposed FE IC, validating the system's reconfigurability and high-linearity. |
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ISSN: | 1549-8328 1558-0806 |
DOI: | 10.1109/TCSI.2019.2943904 |