Self-timed Fused Multiply-add Unit Performance Improvement

The paper presents the results of researching and developing methods accelerating a self-timed unit that performs a fused multiply-add-subtract operation under three operands following the IEEE754 standard. The paper proposes a normalization order of the sum and difference speculative estimation whe...

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Bibliographic Details
Published in2022 Conference of Russian Young Researchers in Electrical and Electronic Engineering (ElConRus) pp. 459 - 463
Main Authors Sokolov, Igor A., Rogdestvenski, Yuri V., Rogdestvenskene, Asta V., Stepchenkov, Yury A., Diachenko, Yuri G., Diachenko, Denis Y.
Format Conference Proceeding
LanguageEnglish
Published IEEE 25.01.2022
Subjects
Costs
Digital signal processing
Encoding
Estimation
fused multiply-add unit
Hardware
indication
Pipelines
precision
self-timed circuit
Signal processing algorithms
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Summary:The paper presents the results of researching and developing methods accelerating a self-timed unit that performs a fused multiply-add-subtract operation under three operands following the IEEE754 standard. The paper proposes a normalization order of the sum and difference speculative estimation when using ternary self-timed coding. This estimation uses a difference of the 24 most significant bits of the product and the third aligned operand for counting leading zeroes. This technique provides a 20% reduction in complexity when implementing the shifter in the normalization block. The analysis shows that the developed methods accelerate the normalization stage by an average of 32% on the statistical set of the input operands.
ISSN:2376-6565
DOI:10.1109/ElConRus54750.2022.9755720