Implementation of Deep Learning Algorithms Through a Module Based Approach Using Multiplierless Architectures

• Published in: 2022 3rd International Conference for Emerging Technology (INCET) pp. 1 - 6
• Main Authors: Eligar, Sanjay, Eligar, Vijaya, Iyer, Nalini
• Format: Conference Proceeding
• Language: English
• Published: IEEE 27.05.2022
• Subjects: Computer architecture; Deep learning; Logic gates; Manchester Carry Chain Adder; Multiplexer; Q15; Roads; Shock absorbers; System-on-chip; Velocity estimation; Very large scale integration
• DOI: 10.1109/INCET54531.2022.9825401

Deep Learning algorithms are enabling the design of complex systems across multiple domains. Conventional implementations of these algorithms relied on GPU based implementations, but for safety-critical applications like autonomous vehicles and smart automotive systems, we need to shift compute-intensive tasks to hardware implementations. VLSI design has been at the forefront of the IT revolution across the world. Applications that otherwise would be at board level are now been integrated into a single System on Chip. This paper discusses the design implementation of an automotive subsystem for smart suspension systems. The need to use a custom VLSI flow is presented and the most commonly used data path element which is a 16-bit Adder is discussed. Manchester Carry Chain Adders are chosen for implementation using a Transmission Gate based logic after considering alternatives like Basic CMOS, Single/Double Gate MOSFET and Gate Diffusion Input. The multiplier-less architecture is implemented using mostly multiplexers and delay elements. The functionality of the controller is validated for application-specific test vectors.