Design and Mathematical Modelling of Inter Spike Interval of Temporal Neuromorphic Encoder for Image Recognition

Neuromorphic computing systems emulate the electrophysiological behavior of the biological nervous system using mixed-mode analog or digital VLSI circuits. These systems show superior accuracy and power efficiency in carrying out cognitive tasks. The neural network architecture used in neuromorphic...

Full description

Saved in:
Bibliographic Details
Published in2020 5th IEEE International Conference on Emerging Electronics (ICEE) pp. 1 - 4
Main Authors VS, Aadhitiya, Shaik, Jani Babu, Singhal, Sonal, Picardo, Siona Menezes, Goel, Nilesh
Format Conference Proceeding
LanguageEnglish
Published IEEE 26.11.2020
Subjects
Circuit simulation
CMOS circuits
Image coding
Image recognition
Image resolution
Mathematical models
Neuromorphic engineering
Neurons
Spiking Neural Network
Temporal Neuromorphic Encoder
Online AccessGet full text

Cover

More Information
Summary:Neuromorphic computing systems emulate the electrophysiological behavior of the biological nervous system using mixed-mode analog or digital VLSI circuits. These systems show superior accuracy and power efficiency in carrying out cognitive tasks. The neural network architecture used in neuromorphic computing systems is spiking neural networks (SNNs) analogous to the biological nervous system. SNN operates on spike trains as a function of time. A neuromorphic encoder converts sensory data into spike trains. In this paper, a low-power neuromorphic encoder for image processing is implemented. A mathematical model between pixels of an image and the inter-spike intervals is also formulated. Wherein an exponential relationship between pixels and inter-spike intervals is obtained. Finally, the mathematical equation is validated with circuit simulation. The circuits in our work, are implemented on industry-standard HKMG based 45nm technology.
DOI:10.1109/ICEE50728.2020.9777025