Negative Bias Temperature Instability Analysis of a 15 nm p-channel Junctionless Fin Field Effect Transistor (p-JLFinFET)

• Published in: 2022 IEEE 20th Student Conference on Research and Development (SCOReD) pp. 73 - 76
• Main Authors: Hamzah, M. Naziiruddin, Alias, N. Ezaila, Peng Tan, M. L.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 08.11.2022
• Subjects: Degradation; Drain Current; Field effect transistors; Fin Field Effect Transistor; Junctionless; Logic gates; NBTI; Negative bias temperature instability; Simulation; Switches; Thermal variables control; Threshold voltage
• ISSN: 2643-2447
• DOI: 10.1109/SCOReD57082.2022.9973446

In this paper, the study of the reliability issue of Negative Bias Temperature Instability (NBTI) on a 15 nm p-channel Junctionless Fin Field Effect Transistor (p-JLFinFET) was analyzed. This work provides inputs on the degradation effect caused by NBTI on the p-JLFinFET which will degrade the electrical parameters of the device. The simulation is done by constructing the p-JLFinFET device structure with a gate length of 15 nm by using Sentaurus TCAD tool, and then applying a stress voltage to the p-JLFinFET's gate terminal to observe the NBTI characteristics. The electrical behavior of the simulated p-JLFinFET was compared with the previous JLFinFET experimental work for device structure validation. Once the device structure is validated, negative stress voltage is applied to the gate terminal of the p-JLFinFET for 10,000 seconds. The electrical parameters before and after stress application were analyzed and compared. Results show under stress application of -1.8V for 10,000s and have been extrapolated up to 10 years by using the power law method, the threshold voltage (\mathrm{V}_{\text{th}}) increased by 15.7 % from its initial value thus causing an increase in the power consumption and slower switching speed of the device.