An Efficient Approximation Look Up Table Based Distributed Arithmetic (DA) VLSI Architecture for Finite Impulse Response

• Published in: 2022 2nd International Conference on Advance Computing and Innovative Technologies in Engineering (ICACITE) pp. 1849 - 1852
• Main Authors: Bhadavath, Kiran kumar, Livinsa, Z. Mary
• Format: Conference Proceeding
• Language: English
• Published: IEEE 28.04.2022
• Subjects: Adaptive filters; Adders; Approximation look up table (ALUT); DAP (Digital Adaptive Filter); Distributed arithmetic (DA); Finite impulse response filters; Hardware design languages; System performance; Table lookup; Very large scale integration; WSAT (Wallace shift adder tree)
• DOI: 10.1109/ICACITE53722.2022.9823908

The proposed composite design uses Distributed Arithmetic (DA) in this work. The DA is a method of putting into practise the inner product of two vectors without using a multiplier. Distributed Arithmetic (DA)-based structures are extensively utilised in DSP applications for high-speed inner product computation. A unique Approximation Look Up Table (ALUT)-based structure based on an effective truncation model has been proposed, and offers more computation compared to existing systems like MAC (Multiply and Accumulate), DA (Distributed Arithmetic), DAP (Digital Adaptive Filter), and WSAT (Wallace Shift Adder Tree). The proposed framework saves nearly 50% more bits than existing structures, while ADP (area-delay product) saves 61 % while producing outputs that are nearly identical to or slightly less efficient than existing structures. The proposed approach boosts system performance while also maximising FPGA utilization. The simulation was carried out using Verilog on a Xilinx ISE 14.7 platform.