Design of Intra Cluster Access Structure for Distributed Caches of Array Processor

Aiming at the requirements of high bandwidth and low latency for memory in reconfigurable computing, and the characteristics of high data parallelism, large access stock, and obvious temporal locality of reconfigurable array processor, an access structure is proposed. Based on the distributed Cache...

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Bibliographic Details
Published in2022 14th International Conference on Measuring Technology and Mechatronics Automation (ICMTMA) pp. 66 - 73
Main Authors Liu, You-Yao, Cai, Hui-Nan, Han, Si-Yi
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.01.2022
Subjects
Array processor
Bandwidth
Distributed
Hardware
Iterative algorithms
Mapping
Memory management
Newton iterative method
Parallel processing
Reconfigurable computing
System-on-chip
Topology
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Summary:Aiming at the requirements of high bandwidth and low latency for memory in reconfigurable computing, and the characteristics of high data parallelism, large access stock, and obvious temporal locality of reconfigurable array processor, an access structure is proposed. Based on the distributed Cache of reconfigurable array processors, this structure realizes the parallel cross memory access of PE in the cluster, solves the problem of serious shortage of storage bandwidth, improves the memory access speed in the cluster, and reduces the memory access power consumption. The FPGA development board is used to verify the prototype of the design. Under the conflict-free memory access, the maximum frequency of parallel read-write memory access of 4 * 4 PE arrays in the cluster reaches 220 MHz, and the peak bandwidth of memory access is 7.53 GB/s. Finally, the mapping of the Newton iterative detection algorithm is completed on this structure. The structure provides 329.44 MB/s data access bandwidth for the algorithm, and the running time is 0.38ms.
ISSN:2157-1481
DOI:10.1109/ICMTMA54903.2022.00020