Single Event Latchup (SEL) and Single Event Upset (SEU) Evaluation of Xilinx 7nm Versal™ ACAP programmable logic (PL)

this paper examines the single-event latchup (SEL) and single event upset (SEU) response of the Xilinx 7nm XCVC1902 ES1 Versal ACAP Programmable Logic irradiated with neutrons and 64 MeV protons sources. No SEL was observed in the entire Xilinx 7nm XCVC1092 for worst case conditions. Furthermore, Th...

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Bibliographic Details
Published in2021 IEEE Nuclear and Space Radiation Effects Conference (NSREC) pp. 1 - 6
Main Authors Maillard, Pierre, Chen, Yanran P., Barton, Jeff, Voogel, Martin L.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.07.2021
Subjects
Conferences
Kintex
Layout
Protons
Random access memory
SEL
SEUs
Single event latchup
Single event upsets
Technological innovation
Versal ACAP
Xilinx 7nm
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Summary:this paper examines the single-event latchup (SEL) and single event upset (SEU) response of the Xilinx 7nm XCVC1902 ES1 Versal ACAP Programmable Logic irradiated with neutrons and 64 MeV protons sources. No SEL was observed in the entire Xilinx 7nm XCVC1092 for worst case conditions. Furthermore, The SEU response for single-event upsets on configuration RAM (CRAM) cells, block RAM (BRAM) and block RAM (BRAM) cells are provided.
DOI:10.1109/NSREC45046.2021.9679343