Design of Energy Efficient Magnitude Comparator Architecture using 8T XOR Gate

• Published in: 2022 3rd International Conference on Electronics and Sustainable Communication Systems (ICESC) pp. 17 - 23
• Main Authors: Naik, Sugali Siva, Basarkod, P I
• Format: Conference Proceeding
• Language: English
• Published: IEEE 17.08.2022
• Subjects: Area and delay; Delays; dynamic power consumption and Analog to Digital converters; Energy efficiency; Frequency modulation; Logic gates; Low Power consumption; Magnitude comparator; Memory management; Power demand; Power dissipation; Power Gating
• DOI: 10.1109/ICESC54411.2022.9885502

This paper proposes a CMOS comparator circuitry with a three-stage topology for a high-speed Analog-to-Digital Converter (ADC). The speed of ADC is limited by the used comparator. Hence, the optimization of the comparator is crucial for a fast ADC. In computationally intensive designs, the use of comparators is inevitable. The optimization of comparator design while maximizing speed, minimizing power dissipation, and minimizing area is needed. Though the dynamic logic-based comparators are successful in minimizing power consumption, they pose challenges such as low-speed and poor-noise margin. In this paper, a low power and area efficient magnitude comparator is designed by utilizing an 8T xor gate. In the proposed xor gate power gating is applied so that the power consumption can be optimized. This proposed low power xor -xnor module is the fundamental circuit in the comparator circuit. Hence, the power consumption of digital comparator is also reduced. The recommended comparator is composed of 2 modules namely, CEM (Comparison Evaluation Module) and the FM (Final Evaluation Module). All the designs are simulated in Tanner EDA tool using 180nm technology.