High Performance Erasure Coding for Very Large Stripe Sizes

Exascale computing demands high bandwidth and low latency I/O on the computing edge. Object storage systems can provide higher bandwidth and lower latencies than tape archive. File transfer nodes present a single point of mediation through which data moving between these storage systems must pass. B...

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Bibliographic Details
Published in2019 Spring Simulation Conference (SpringSim) pp. 1 - 12
Main Authors Haddock, Walker, Bangalore, Purushotham V., Curry, Matthew L., Skjellum, Anthony
Format Conference Proceeding
LanguageEnglish
Published SCS 01.04.2019
Subjects
Bandwidth
Computer architecture
Distributed databases
Encoding
erasure coding
fault tolerance
GPGPU
Graphics processing units
Libraries
object
resilience
storage
Supercomputers
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Summary:Exascale computing demands high bandwidth and low latency I/O on the computing edge. Object storage systems can provide higher bandwidth and lower latencies than tape archive. File transfer nodes present a single point of mediation through which data moving between these storage systems must pass. By increasing the performance of erasure coding, stripes can be subdivided into large numbers of shards.This paper's contribution is a prototype nearline disk object storage system based on Ceph. We show that using general purpose graphical processing units (GPGPU) for erasure coding on file transfer nodes is effective when using a large number of shards. We describe an architecture for nearline disk archive storage for use with high performance computing (HPC) and demonstrate the performance with benchmarking results. We compare the benchmark performance of our design with the Intel®Storage Acceleration Library (ISA-L) CPU based erasure coding libraries using the native Ceph erasure coding feature.
DOI:10.23919/SpringSim.2019.8732912