A Flexible Power Control Method for Right Power Testing of Scan-Based Logic BIST

High power dissipation during scan-based logic BIST is a crucial problem that leads to over-testing. Although controlling test power of a circuit under test (CUT) to an appropriate level is strongly required, it is not easy to control test power in BIST. This paper proposes a novel power controlling...

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Bibliographic Details
Published in2016 IEEE 25th Asian Test Symposium (ATS) pp. 203 - 208
Main Authors Kato, Takaaki, Wang, Senling, Sato, Yasuo, Kajihara, Seiji, Wen, Xiaoqing
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.11.2016
Subjects
Built-in self-test
Circuit faults
logic BIST
Logic gates
low power test
Power control
pseudo random pattern
scan design
scan shift power control
Switches
Timing
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Summary:High power dissipation during scan-based logic BIST is a crucial problem that leads to over-testing. Although controlling test power of a circuit under test (CUT) to an appropriate level is strongly required, it is not easy to control test power in BIST. This paper proposes a novel power controlling method to control the toggle rate of the patterns to an arbitrary level by modifying pseudo random patterns generated by a TPG (Test Pattern Generator) of logic BIST. While many approaches have been proposed to control the toggle rate of the patterns, the proposed approach can provide higher fault coverage. Experimental results show that the proposed approach can control toggle rates to a predetermined target level and modified patterns can achieve high fault coverage without increasing test time.
ISSN:2377-5386
DOI:10.1109/ATS.2016.59