Modeling of glitch effects in FPGA based arithmetic circuits

• Published in: 2006 IEEE International Conference on Field Programmable Technology pp. 349 - 352
• Main Authors: Gaffar, A.A., Clarke, J.A., Constantinides, G.A.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.12.2006
• Subjects: Arithmetic; Capacitance; Costs; Digital circuits; Educational institutions; Energy consumption; Field programmable gate arrays; Logic circuits; Logic devices; Power engineering and energy
• ISBN: 0780397282; 9780780397286
• DOI: 10.1109/FPT.2006.270345

One of the requirements when using high-level power optimization techniques is the ability to estimate circuit power consumption quickly. Bit-level estimation techniques which take into account the glitch activity in a circuit take too long to provide power estimates. In this paper we present a novel method which can provide fast estimates for the logic and intra-routing power consumption in digital circuits whilst taking into account the glitch activity but relying purely on the word-level statistics of the signals. The proposed method models the propagation of glitch activity in signals through the arithmetic components in circuits, and using this information estimates the logic and intra-routing power consumption. For arithmetic circuits implemented on FPGAs we demonstrate that previous macro-model based power estimation techniques consistently under-estimate the power consumption by up to 20 times, whilst this work can provide estimates to within a mean relative error of 30% compared to low-level power estimation