Scalability of 3D-Integrated Arithmetic Units in High-Performance Microprocessors

Three-dimensional integration provides a simultaneous improvement in wire-related delay and power consumption of microprocessor circuits. Prior work has looked at the performance, power, and area benefits of the 3D integration technology. In this paper, we investigate the scalability issues of 3D di...

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Bibliographic Details
Published in2007 44th ACM/IEEE Design Automation Conference pp. 622 - 625
Main Authors Puttaswamy, K., Loh, G.H.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.06.2007
Subjects
Circuits
Clocks
Delay
Design
Die-stacked 3D integration
Digital arithmetic
Energy consumption
Issue-width
Microprocessors
Parallel processing
Power engineering computing
Scalability
Temperature sensors
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Summary:Three-dimensional integration provides a simultaneous improvement in wire-related delay and power consumption of microprocessor circuits. Prior work has looked at the performance, power, and area benefits of the 3D integration technology. In this paper, we investigate the scalability issues of 3D die-stacked arithmetic units. We explore the behavior of the 3D-integrated arithmetic circuits with increasing issue- width (parallel execution capability), transistor sizing, and temperature. We show that the 3D-integrated units have a lower latency degradation and lower rate of increase in energy consumption than the planar circuits with increasing issue-widths and operating temperatures. We demonstrate that the 3D-integrated circuits have less sensitivity to transistor sizing than the planar circuits.
ISBN:1595936270
9781595936271
ISSN:0738-100X
DOI:10.1109/DAC.2007.375238