Simultaneous scheduling and binding for resource usage and interconnect complexity reduction in high-level synthesis

This paper proposes a simultaneous scheduling and binding approach for resource and interconnect reduction in high-level synthesis. The scheme incorporates the operation scheduling into functional unit (FU) and register binding, targeting the reduction of both resource and interconnect reduction. A...

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Bibliographic Details
Published inProceedings (International Conference on ASIC) pp. 1 - 4
Main Authors Cong Hao, Jian-Mo Ni, Hui-Tong Wang, Yoshimura, Takeshi
Format Conference Proceeding Journal Article
LanguageEnglish
Published IEEE 01.11.2015
Subjects
Algorithm design and analysis
Algorithms
Binding
Buildings
Complexity theory
Conferences
Electronics
Interconnections
Multiplexing
Optimized production technology
Reduction
Registers
Scheduling
Synthesis
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Summary:This paper proposes a simultaneous scheduling and binding approach for resource and interconnect reduction in high-level synthesis. The scheme incorporates the operation scheduling into functional unit (FU) and register binding, targeting the reduction of both resource and interconnect reduction. A simplified weighted and ordered compatibility graph (SWOCG) based binding algorithm is also proposed and runs tens of times faster than the WOCG based binding algorithm. The experimental results show that our proposal achieves 4% to 15% reduction in resource usage and interconnect reduction, and also runs 5X faster compared to previous works.
Bibliography:ObjectType-Article-2
SourceType-Scholarly Journals-1
ObjectType-Conference-1
ObjectType-Feature-3
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SourceType-Conference Papers & Proceedings-2
ISBN:9781479984831
1479984833
ISSN:2162-755X
DOI:10.1109/ASICON.2015.7516908