Influence of plasma edge damage on erase characteristics of NOR flash EEPROM using channel erase method

• Published in: 2002 IEEE International Reliability Physics Symposium. Proceedings. 40th Annual (Cat. No.02CH37320) pp. 354 - 358
• Main Authors: Dong-Kyu Lee, Lee, W.H., Young-Ho Na, Keon-Soo Kim, Kun-Ok Ahn, Kang-Deog Suh, Yonghan Roh
• Format: Conference Proceeding
• Language: English
• Published: Piscataway NJ IEEE 2002
• Subjects: Applied sciences; Design. Technologies. Operation analysis. Testing; Electronics; Electrons; EPROM; Etching; Exact sciences and technology; Integrated circuits; Microelectronic fabrication (materials and surfaces technology); Nonvolatile memory; Plasma applications; Plasma devices; Plasma materials processing; Plasma properties; Plasma sources; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Testing, measurement, noise and reliability; Tunneling; Waveform; Defect density; Erasure; Experimental study; NOR circuit; Microelectronic fabrication; EEPROM memory; Experimental result; Edge effect; Flash memory; Gate oxide; Failure analysis; Plasma etching; Transistor channel; Integrated circuit; Measurement method; Reliability
• ISBN: 0780373529; 9780780373525
• DOI: 10.1109/RELPHY.2002.996659

We report the impact of plasma edge damage on erase characteristics in NOR Flash cells where channel erase is employed. Anomalous over-erased bits were observed, and they appeared to be associated with the creation of positive traps near the floating gate edge in the tunneling oxide layer during the plasma etch process. By examining possible processes and analyzing the erase characteristics, we have concluded that plasma edge damage is the cause of the anomalous erase behavior. Since the size of the damaged region does not decrease as the stacked gate channel length is scaled down, we foresee this defect as a serious limitation to future devices, especially Flash EEPROM.