Memory-Access Optimization for Acceleration and Power Saving of FPGA-Based Image Processing

In this paper, we propose a method for acceleration and power saving of FPGA-based image processing by optimizing memory access. The BRAM-based System can improve the datatransmission speed between the FPGA and memory device by storing the image-processed data in BRAM. Also, it does not require an a...

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Bibliographic Details
Published in2022 19th International SoC Design Conference (ISOCC) pp. 338 - 339
Main Authors Shimohane, Shungo, Inoue, Toshiyuki, Tsuchiya, Akira, Kishine, Keiji
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.01.2022
Subjects
Field programmable gate arrays
Image processing
Logic circuits
Optimization
Power demand
Resource management
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Summary:In this paper, we propose a method for acceleration and power saving of FPGA-based image processing by optimizing memory access. The BRAM-based System can improve the datatransmission speed between the FPGA and memory device by storing the image-processed data in BRAM. Also, it does not require an additional driver to absorb the latency, which leads to reducing the hardware-resource usage and the power consumption. Our memory-access optimization enables that the processing speed is increased by about 9 times and the power consumption is reduced by 10% compared to that of the conventional DRAMbased system.
DOI:10.1109/ISOCC56007.2022.10031293