Simulation-based diagnosis for crosstalk faults in sequential circuits

• Published in: Proceedings - Asian Test Symposium pp. 63 - 68
• Main Authors: Takahashi, H., Phadoongsidhi, M., Higami, Y., Saluja, K.K., Takamatsu, Y.
• Format: Conference Proceeding Journal Article
• Language: English
• Published: IEEE 2001
• Subjects: Central Processing Unit; Circuit faults; Circuit simulation; Circuit testing; Clocks; Computational modeling; Crosstalk; Fault diagnosis; Pulse circuits; Sequential circuits
• ISBN: 9780769513782; 0769513786
• ISSN: 1081-7735; 2377-5386
• DOI: 10.1109/ATS.2001.990260

Describes two methods of diagnosing crosstalk-induced pulse faults in sequential circuits using crosstalk fault simulation. These methods compare with observed responses and simulated values at primary outputs to identify a set of suspected faults that are consistent with the observed responses. In these methods, if the simulated values agree with the observed responses, then the simulated fault is added to a set of suspected faults, otherwise the simulated fault is removed from the set of suspected faults. The diagnosis methods repeat the above process for each time frame to identify the suspected faults. The first method is a basic method which determines the suspected fault list by using the knowledge about the first and last failures of the test sequence. The second method uses state information and focuses on reducing the CPU time for diagnosing the faults. The CPU time is reduced by using stored state information to calculate the primary output values at the present time frame. Experimental results for ISCAS'89 benchmark circuits show that the number of suspected faults obtained by our methods is sufficiently small, and the second method is substantially faster than the first method.