A split transconductor high-speed SAR ADC

A feasibility study of an 8-bit fast converter is presented. The advantages and limits of conventional SAR architectures are discussed and, on the basis of that, a possible optimal architecture is proposed. It uses a 4+4-bit scheme with combination of the DAC outputs in the current domain at the inp...

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Bibliographic Details
Published in2015 IEEE International Symposium on Circuits and Systems (ISCAS) pp. 2433 - 2436
Main Authors Muratore, Dante Gabriel, Bonizzoni, Edoardo, Maloberti, Franco
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.05.2015
Subjects
Arrays
Capacitance
Capacitors
CMOS integrated circuits
Latches
Topology
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Summary:A feasibility study of an 8-bit fast converter is presented. The advantages and limits of conventional SAR architectures are discussed and, on the basis of that, a possible optimal architecture is proposed. It uses a 4+4-bit scheme with combination of the DAC outputs in the current domain at the input of the latch. The circuit has been implemented with a 28 nm FDSOI CMOS technology. Post layout simulation results show 8bit of resolution at 1.2 GS/s.
ISSN:0271-4302
2158-1525
DOI:10.1109/ISCAS.2015.7169176