Parallel pipelined histogram architecture via C-slow retiming

A parallel pipelined array of cells suitable for realtime computation of histograms is proposed. The cell architecture builds on previous work to now allow operating on a stream of data at 1 pixel per clock cycle. This new cell is more suitable for interfacing to camera sensors or to microprocessors...

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Published in2013 IEEE International Conference on Consumer Electronics (ICCE) pp. 230 - 231
Main Authors Cadenas, J. O., Sherratt, R. S., Huerta, P., Wen-Chung Kao, Megson, G.
Format Conference Proceeding Journal Article
LanguageEnglish
Published IEEE 01.01.2013
Subjects
Adders
Architecture
Arrays
Clocks
Conferences
Construction
Consumption
Data buses
Histograms
Registers
Sensors
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Summary:A parallel pipelined array of cells suitable for realtime computation of histograms is proposed. The cell architecture builds on previous work to now allow operating on a stream of data at 1 pixel per clock cycle. This new cell is more suitable for interfacing to camera sensors or to microprocessors of 8-bit data buses which are common in consumer digital cameras. Arrays using the new proposed cells are obtained via C-slow retiming techniques and can be clocked at a 65% faster frequency than previous arrays. This achieves over 80% of the performance of two-pixel per clock cycle parallel pipelined arrays.
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SourceType-Conference Papers & Proceedings-2
ISBN:1467313610
9781467313612
ISSN:2158-3994
2158-4001
DOI:10.1109/ICCE.2013.6486871