Performance and interface buffer size driven behavioral partitioning for embedded systems

• Published in: Proceedings. Ninth International Workshop on Rapid System Prototyping (Cat. No.98TB100237) pp. 116 - 121
• Main Authors: Ta-Cheng Lin, Sait, S.M., Cyre, W.R.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 1998
• Subjects: Communication system control; Control systems; Cost function; Data analysis; Delay estimation; Delay systems; Flow graphs; Partitioning algorithms; Pattern analysis; Size control
• ISBN: 0818684798; 9780818684791
• ISSN: 1074-6005; 2332-6581
• DOI: 10.1109/IWRSP.1998.676679

One of the major differences in partitioning for co-design is in the way the communication cost is evaluated. Generally, the size of the edge cut-set is used. When communication between components is through buffered channels, the size of the edge cut-set is not adequate to estimate the buffer size. A second important factor to measure the quality of partitioning is the system delay. Most partitioning approaches use the number of nodes/functions in each partition as constraints and attempt to minimize the communication cost. The data dependencies among nodes/functions and their delays are not considered. In this paper, we present partitioning with two objectives: (1) buffer size, which is estimated by analyzing the data flow patterns of the control data flow graph (CDFG) and solved as a clique partitioning problem, and (2) the system delay that is estimated using list scheduling. We pose the problem as a combinatorial optimization and use an efficient non-deterministic search algorithm, called the problem-space genetic algorithm, to search for the optimum. Experimental results indicate that, according to a proposed quality metric, our approach can attain an average 87% of the optimum for two-way partitioning.