Sensitivity analysis of a technique for the extraction of interface trap density in SiC MOSFETs from subthreshold characteristics

A method for extracting interface trap density (DIT) from subthreshold I-V characteristics is used to analyze data on a SiC MOSFET stressed for thirty minutes at 175°C with a gate bias of -20 V. Without knowing the channel doping, the change in D IT can be calculated when referenced to an energy lev...

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Bibliographic Details
Published in2014 IEEE International Reliability Physics Symposium pp. 2C.2.1 - 2C.2.6
Main Authors Hughart, D. R., Flicker, J. D., Atcitty, S., Marinella, M. J., Kaplar, R. J.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.06.2014
Subjects
Doping
elevated temperature
Energy states
interface traps
MOSFET
power electronics
reliability
Silicon carbide
Stress
subthreshold slope
Threshold voltage
Transconductance
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Summary:A method for extracting interface trap density (DIT) from subthreshold I-V characteristics is used to analyze data on a SiC MOSFET stressed for thirty minutes at 175°C with a gate bias of -20 V. Without knowing the channel doping, the change in D IT can be calculated when referenced to an energy level correlated with the threshold voltage.
ISSN:1541-7026
1938-1891
DOI:10.1109/IRPS.2014.6860589