An FPGA-based all-digital 802.11b & 802.15.4 receiver for the Software Defined Radio paradigm

An FPGA implementation of an all-digital fully compliant IEEE 802.11b and 802.15.4 configurable baseband receiver is presented. This architecture can be integrated in systems implementing the Software Defined Radio (SDR) paradigm, relaxing the need for high power consumption general purpose processo...

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Bibliographic Details
Published in2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14) pp. 1 - 6
Main Authors Espinoza-Rhoton, Alfredo, Gonzalez-Perez, Luis F., Ponce, J. L., Hector, Borrayo S., C.-Yllescas, Lennin, Parra-Michel, R., Aboushady, Hassan
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.12.2014
Subjects
Baseband
digital receivers
Field programmable gate arrays
FPGA
IEEE 802.15 Standards
Phase shift keying
QPSK
Receivers
reconfigurable receiver
Software Defined Radio
VLSI
WiFi
ZigBee
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Summary:An FPGA implementation of an all-digital fully compliant IEEE 802.11b and 802.15.4 configurable baseband receiver is presented. This architecture can be integrated in systems implementing the Software Defined Radio (SDR) paradigm, relaxing the need for high power consumption general purpose processors. The receiver uses a single architecture that can be configured for receiving either standard at run time, exploiting similarities between both protocols, and may serve as a coprocessor for offloading the task of processing baseband RF signals. The system can be used as a platform for future low power devices to integrate into the SDR paradigm. Results showed that the architecture exceeds the specifications required by both standards, and has great performance in low SNR scenarios, making it an attractive alternative in wireless sensor networks with extremely low signal power levels.
ISSN:2325-6532
2640-0472
DOI:10.1109/ReConFig.2014.7032499