A Re-configurable 0.5V to 1.2V, 10MS/s to 100MS/s, Low-Power 10b 0.13um CMOS Pipeline ADC

This work describes a re-configurable 0.5 V to 1.2 V, 10 MS/s to 100 MS/s, 10 b two-step pipeline ADC. The prototype ADC in a 0.13 um CMOS process demonstrates the measured DNL and INL within 0.35 LSB and 0.49 LSB, respectively. The ADC with an active die area of 0.98 mm 2 shows the maximum SNDR and...

Full description

Saved in:
Bibliographic Details
Published in2007 IEEE Custom Integrated Circuits Conference pp. 185 - 188
Main Authors Young-Ju Kim, Hee-Cheol Choi, Si-Wook Yoo, Seung-Hoon Lee, Dae-Young Chung, Kyoung-Ho Moon, Ho-Jin Park, Jae-Whui Kim
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.09.2007
Subjects
Clocks
CMOS logic circuits
Digital circuits
Energy consumption
Pipelines
Power supplies
Prototypes
Switches
System-on-a-chip
Voltage
Online AccessGet full text

Cover

More Information
Summary:This work describes a re-configurable 0.5 V to 1.2 V, 10 MS/s to 100 MS/s, 10 b two-step pipeline ADC. The prototype ADC in a 0.13 um CMOS process demonstrates the measured DNL and INL within 0.35 LSB and 0.49 LSB, respectively. The ADC with an active die area of 0.98 mm 2 shows the maximum SNDR and SFDR of 56.0 dB and 69.6 dB, respectively, and a power consumption of 19.2 mW at a nominal condition of 0.8 V and 60 MS/s.
ISBN:9781424407866
1424407869
ISSN:0886-5930
2152-3630
DOI:10.1109/CICC.2007.4405709