An approach for a dynamic generation/validation system for the functional simulation considering timing constraints

This paper presents a method for the automatic validation of the timing behavior of RT and gate level VHDL descriptions. Using a machine-readable timing specification, we automatically create a VHDL testbench for the stimuli generation and the validation of the expected responses. We have developed...

Full description

Saved in:
Bibliographic Details
Published inProceedings - European Conference on Design Automation pp. 302 - 306
Main Authors Heinkel, U., Glauert, W.H.
Format Conference Proceeding
LanguageEnglish
Published IEEE 1996
Subjects
Application specific integrated circuits
Automatic testing
Circuit simulation
Circuit synthesis
Computational modeling
Computer simulation
Integrated circuit modeling
Integrated circuit synthesis
Packaging machines
Timing
Online AccessGet full text

Cover

More Information
Summary:This paper presents a method for the automatic validation of the timing behavior of RT and gate level VHDL descriptions. Using a machine-readable timing specification, we automatically create a VHDL testbench for the stimuli generation and the validation of the expected responses. We have developed a VHDL package using linear programming algorithms to compute a valid set of stimuli. The model responses are checked dynamically subject to the model outputs. A graphical interface is used to specify and validate a timing diagram.
ISBN:9780818674242
0818674245
ISSN:1066-1409
DOI:10.1109/EDTC.1996.494317