Low-cost TSV process using electroless Ni plating for 3D stacked DRAM

• Published in: 2010 Proceedings 60th Electronic Components and Technology Conference (ECTC) pp. 1094 - 1099
• Main Authors: Kawano, Masaya, Takahashi, Nobuaki, Komuro, Masahiro, Matsui, Satoshi
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.01.2010
• Subjects: Annealing; Costs; DRAM chips; Fabrication; Gold; Large scale integration; Nickel; Palladium; Random access memory; Through-silicon vias
• ISBN: 9781424464104; 1424464102
• ISSN: 0569-5503; 2377-5726
• DOI: 10.1109/ECTC.2010.5490838

Three-dimensional integration using through-silicon vias (TSVs) has been widely developed. However, the additional cost of fabricating TSVs is one of the main factors that prevent the use of TSVs in large-scale integrated circuits (LSIs). In this paper, we propose a new and inexpensive TSV process in which TSVs and back-bumps are simultaneously fabricated using electroless nickel electroless palladium immersion gold plating. During this process, Ni is plated onto W pads on the back of Si. We successfully fabricated uniform TSVs and back-bumps by optimizing the fabrication process, which included implementing light-shield plating and performing annealing after plating. We fabricated two types of eight-stacked dynamic random access memories (DRAMs), one using poly-Si TSVs and one using Ni TSVs, and compared the operation of each type of DRAM.