DPPM Reduction Methods and New Defect Oriented Test Methods Applied to Advanced FinFET Technologies

This paper presents DPPM reduction results achieved with new Defect Oriented Test (DOT) methods/patterns applied to designs manufactured in advanced FinFET technologies. Focus of this paper is on Timing-Aware Cell-Aware Test (TA-CAT) patterns targeting small-delay defects of FinFET transistors, and...

Full description

Saved in:
Bibliographic Details
Published in2018 IEEE International Test Conference (ITC) pp. 1 - 10
Main Authors Howell, W., Hapke, F., Brazil, E., Venkataraman, S., Datta, R., Glowatz, A., Redemund, W., Schmerberg, J., Fast, A., Rajski, J.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.10.2018
Subjects
Cats
Delays
FinFETs
Image edge detection
Layout
Online AccessGet full text

Cover

More Information
Summary:This paper presents DPPM reduction results achieved with new Defect Oriented Test (DOT) methods/patterns applied to designs manufactured in advanced FinFET technologies. Focus of this paper is on Timing-Aware Cell-Aware Test (TA-CAT) patterns targeting small-delay defects of FinFET transistors, and a new DOT method which explicitly targets chip layout dependent cell-neighborhood defects. Test results from traditional Stuck-at/Transition patterns, from traditional CAT patterns, from TA-CAT patterns, and as well from cell-neighborhood patterns, applied to FinFET technology designs, will be presented in this paper. In addition, a correlation to System-Level-Test fails will be discussed.
ISSN:2378-2250
DOI:10.1109/TEST.2018.8624906