Novel thinning/backside passivation for substrate coupling depression of 3D IC

• Published in: 2011 IEEE 61st Electronic Components and Technology Conference (ECTC) pp. 1395 - 1399
• Main Authors: Woonseong Kwon, Jaesik Lee, Lee, V., Seetoh, J., Yenchen Yeo, YeeMong Khoo, Ranganathan, N., Keng Hwa Teo, Shan Gao
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.05.2011
• Subjects: Copper; Dielectrics; Insulation; Passivation; Silicon; Three dimensional displays; Through-silicon vias
• ISBN: 1612844979; 9781612844978
• ISSN: 0569-5503; 2377-5726
• DOI: 10.1109/ECTC.2011.5898694

The building blocks of the 3-D IC integration technology are Through-Silicon Via (TSV) fabrication/implementation, thin wafer handling, low-temperature backside TSV revealing process, and electrical redistribution or connection of vertical circuitry or ICs. Of these elements, the scheme for wafer thinning and backside passivation is a crucial technology element of 3D integration. In this paper, novel backside via revealing and passivation for 3D IC application is proposed with newly developed process integration. Si/Cu CMP process is applied to overcome the practical limitations on the uniformity of the backside thinning originated from the blind thinning process. As such, the height variations associated with via etch non-uniformity and glue, carrier and grinding TTV's (Total Thickness Variation) are flattened out. In order to protrude the TSV from the backside, we demonstrated new spin wet etchback process with well-controlled repeatability, reduced process defect and copper contamination. For the low-k thick dielectric layer application (without photo-litho), Insulation layer on the back side is deposited over the protruded portion of the TSV structure. The deposited insulation layer is removed and TSV area is again exposed. The process for removing this insulation layer is the plasma etching or CMP polish.