Process Optimization of Perpendicular Magnetic Tunnel Junction Arrays for Last-Level Cache beyond 7 nm Node

This paper demonstrates systematic process optimization of perpendicular magnetic tunnel junction (pMTJ) by hardware, unit-process, and material stack design. TMR of 200% at RA 5 Ohm*µm 2 , H SAF ~ 8 kOe, and 10-time tunability of Hc were achieved at the film level. After patterning, 10 −6 write err...

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Bibliographic Details
Published in2018 IEEE Symposium on VLSI Technology pp. 117 - 118
Main Authors Xue, Lin, Ching, Chi, Kontos, Alex, Ahn, Jaesoo, Wang, Xiaodong, Whig, Renu, Tseng, Hsin-wei, Howarth, James, Hassan, Sajjad, Chen, Hao, Bangar, Mangesh, Liang, Shurong, Wang, Rongjun, Pakala, Mahendra
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.06.2018
Subjects
Couplings
Error analysis
Magnetic tunneling
Optimization
Performance evaluation
Tunneling magnetoresistance
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ISSN2158-9682
DOI10.1109/VLSIT.2018.8510642

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Summary:This paper demonstrates systematic process optimization of perpendicular magnetic tunnel junction (pMTJ) by hardware, unit-process, and material stack design. TMR of 200% at RA 5 Ohm*µm 2 , H SAF ~ 8 kOe, and 10-time tunability of Hc were achieved at the film level. After patterning, 10 −6 write error rate was reached at 0.4 pJ, V BD was as high as 1600 mV at 20 ns pulse width, and excellent device stability against 400°C BEOL baking was demonstrated. The device performance along with the process capability to make MTJ array at 88 nm pitch provides opportunities for LLC applications.
ISSN:2158-9682
DOI:10.1109/VLSIT.2018.8510642