Boolean and non-boolean nearest neighbor architectures for out-of-plane nanomagnet logic

• Published in: 2012 13th International Workshop on Cellular Nanoscale Networks and their Applications pp. 1 - 6
• Main Authors: Niemier, M., Csaba, G., Dingler, A., Hu, X. S., Porod, W., Ju, X., Becherer, M., Schmitt-Landsiedel, D., Lugli, P.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.08.2012
• Subjects: Clocks; CMOS integrated circuits; Computer architecture; Hardware; Logic gates; Magnetization; Switches
• ISBN: 9781467302876; 1467302872
• ISSN: 2165-0144; 2165-0152
• DOI: 10.1109/CNNA.2012.6331413

We present the design and simulation of information processing hardware that is comprised of single domain, Co/Pt magnets (i.e., out-of-plane nanomagnet logic - or oNML). We first describe the design and evaluation of oNML hardware that can identify instances of a preprogrammed bit sequence in streaming data. Systolic arrays (that process information using Boolean logic gates) are employed as a system-level architecture which can (i) mitigate less desirable features of the oNML device architecture (nearest neighbor dataflow and longer device switching times when compared to a CMOS transistor), and (ii) exploit unique features of the device architecture (non-volatility and inherently pipelined logic with no overhead). We conclude the paper with a discussion as to how oNML might be employed for non-Boolean information processing. A simple image processing function is used as an initial case study.