Defect-robust FPGA architectures for intellectual property cores in system LSI

• Published in: 2013 23rd International Conference on Field programmable Logic and Applications pp. 1 - 7
• Main Authors: Amagasaki, Motoki, Inoue, Kazuki, Qian Zhao, Iida, Masahiro, Kuga, Morihiro, Sueyoshi, Toshinori
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.09.2013
• Subjects: Arrays; Circuit faults; Fault tolerance; Fault tolerant systems; Field programmable gate arrays; Routing; Tiles
• ISSN: 1946-147X; 1946-1488
• DOI: 10.1109/FPL.2013.6645499

In this paper, we propose fault-tolerant field-programmable gate array (FPGA) architectures and their computer-aid design (CAD) for intellectual property (IP) cores in system large-scale integration (LSI). Unlike discrete FPGAs, in which the integration scale can be made relatively large, programmable IP cores must correspond to arrays of various sizes. The key features of our architectures are regular tile structure, spare modules and bypass wires for fault avoidance, and configuration mechanism for single-cycle reconfiguration. In addition, we develop routing tools, namely EasyRouter for proposed architecture. This tool can handle various array sizes corresponding to developed programmable IP cores. In this evaluation, we compared the performances of conventional FPGA and the proposed fault-tolerant FPGA architectures. On average, our architectures have less than 2.2 times the area and 1.3 times the delay compared with conventional FPGA architectures. At the same time, conventional FP-GAs cannot tolerate faults, whereas our architectures perform with a 90% success rate in fault avoidance for a ratio of faulty tiles of 1% or less.