Enabling Chip-to-Substrate All-Cu Interconnections: Design of Engineered Bonding Interfaces for Improved Manufacturability and Low-Temperature Bonding

• Published in: 2017 IEEE 67th Electronic Components and Technology Conference (ECTC) pp. 968 - 975
• Main Authors: Shahane, Ninad, Mohan, Kashyap, Raj, P. M., Smet, Vanessa, Tummala, Rao, Antoniou, Antonia, Ramos, Gustavo, Taylor, Robin, Kilian, Arnd, Wei, Frank
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.05.2017
• Subjects: Bonding; coarsening etc; Cu interconnections; fine pitch; flipchip bonding; Gold; nanocopper; nanoporous Cu; Oxidation; planarization; Reliability; Rough surfaces; sintering; surface finish; Surface finishing; thermocompression
• ISSN: 2377-5726
• DOI: 10.1109/ECTC.2017.313

This paper presents the design and implementation of engineered nanoscale bonding interfaces as an effective strategy to improve manufacturability of Cu-Cu bonding to the level where it can, for the first time, be applied to chip-to-substrate (C2S) assembly. All-Cu interconnections are highly sought after to meet the escalating electrical, thermal, and reliability requirements of a wide range of emerging digital and analog systems. Such applications require low-cost processes with bonding temperatures and pressures ideally below 200°C and 20MPa, respectively, far from existing solutions established in wafer-level packaging. GT-PRC and its industry partners address this technology gap through innovative designs of bonding interfaces, introducing: 1) novel ultra-thin surface finish metallurgies applied on Cu bumps and pads to prevent oxidation and achieve low-temperature assembly, 2) low-cost fly-cut planarization technique to lower bonding pressures, and 3) low-modulus nanocopper foam caps to provide tolerance to non-coplanarities, and further reduce bonding temperatures and pressures.