Improving the Robustness of a Softcore Processor against SEUs by Using TMR and Partial Reconfiguration

• Published in: 2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines pp. 47 - 54
• Main Authors: Ichinomiya, Yoshihiro, Tanoue, Shiro, Amagasaki, Motoki, Iida, Masahiro, Kuga, Morihiro, Sueyoshi, Toshinori
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.01.2010
• Subjects: Circuit faults; ECC; Field programmable gate arrays; Frequency synchronization; Partial Reconfiguration; Radiation effects; Random access memory; Redundancy; Robustness; Sequential circuits; SEU; Single event transient; Single event upset; Softcore Processor; TMR
• ISBN: 9781424471423; 0769540562; 9780769540566; 1424471427
• DOI: 10.1109/FCCM.2010.16

SRAM-based field programmable gate arrays (FPGAs) are vulnerable to a single event upset (SEU), which is induced by radiation effect. This paper presents a technique for ensuring reliable softcore processor implementation on SRAM-based FPGAs. Although an FPGA is susceptible to SEUs, these faults can be corrected as a result of its reconfigurability. We propose techniques for SEU mitigation and recovery of a softcore processor using triple modular redundancy (TMR) and partial reconfiguration (PR) with state synchronization. By carrying out an experiment, we confirm that a faulty softcore processor can be recovered and synchronized with other softcore processors. The proposed technique requires 4.315 times the resource usage and 62.491% of the operating frequency of the base processor. However, the proposed recovery process only takes 6 μs under TMR and PR. As a result of reliability estimation, the proposed system achieved about 2.713 times longer MTBF comparing with the previous system.