In-situ jitter tolerance measurement technique for Serial I/O

A 10.2-12.5 Gb/s CDR incorporating an on-die jitter modulation circuit that enables in-situ jitter tolerance testing is demonstrated in 65 nm CMOS. Sinusoidal jitter is introduced into the CDR loop by modulating the control voltage of the LC-VCO and is programmable in amplitude and frequency. The mo...

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Bibliographic Details
Published in2008 IEEE Symposium on VLSI Circuits pp. 168 - 169
Main Authors Jaussi, J.E., Balamurugan, G., Kennedy, J., O'Mahony, F., Mansuri, M., Mooney, R., Casper, B., Un-Ku Moon
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.06.2008
Subjects
CDR
Clocks
Frequency measurement
Frequency modulation
Jitter
jitter tolerance
Modulation
self-test and in-situ testing
Serial I/O
Testing
Voltage-controlled oscillators
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Summary:A 10.2-12.5 Gb/s CDR incorporating an on-die jitter modulation circuit that enables in-situ jitter tolerance testing is demonstrated in 65 nm CMOS. Sinusoidal jitter is introduced into the CDR loop by modulating the control voltage of the LC-VCO and is programmable in amplitude and frequency. The modulation frequency range is 340 kHz-104 MHz with modulation amplitudes up to 44 UIpp. The on-die jitter tolerance measurements correlate to conventional external jitter tolerance results within 10% across a 0.73-23.5 MHz range.
ISBN:1424418046
9781424418046
ISSN:2158-5601
2158-5636
DOI:10.1109/VLSIC.2008.4585993