DfT architecture and ATPG for Interconnect tests of JEDEC Wide-I/O memory-on-logic die stacks

• Published in: 2012 IEEE International Test Conference pp. 1 - 10
• Main Authors: Deutsch, S., Keller, B., Chickermane, V., Mukherjee, S., Sood, N., Goel, S. K., Chen, J., Mehta, A., Lee, F., Marinissen, E. J.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.11.2012
• Subjects: Integrated circuit interconnections; Pins; Probes; Random access memory; Stacking; Testing
• ISBN: 146731594X; 9781467315944
• ISSN: 1089-3539; 2378-2250
• DOI: 10.1109/TEST.2012.6401569

Three-dimensional (3D) die stacking is an emerging integration technology which brings benefits with respect to heterogeneous integration, inter-die interconnect density, performance, and energy efficiency, and component size and yield. In the past, we have described, for logic-on-logic die stacks, a 3D DfT (Design-for-Test) architecture and corresponding automation, based on die-level wrappers. Memory-on-logic stacks are among the first 3D products that will come to the market. Recently, JEDEC has released a standard for stackable Wide-I/O Mobile DRAMs (Dynamic Random Access Memories) which specifies the logic-memory interface. The standard includes boundary scan features in the DRAM memories. In this paper, we leverage and extend the 3D DfT wrapper for logic dies, such that, in conjunction with the boundary scan features in the Wide-I/O DRAM(s) stacked on top of it, testing the logic-memory interconnects is enabled. A dedicated Interconnect ATPG (Automatic Test Pattern Generation) algorithm is used to deliver effective and efficient dedicated test patterns. We have verified our proposed DfT extension on an industrial design and shown that the silicon area cost of the extended wrapper with JEDEC Wide-I/O interconnect test support is negligible.