New Generation Dynamically Reconfigurable Processor Technology for Accelerating Embedded AI Applications

We have developed 3rd generation DRP, dynamically reconfigurable processor, for accelerating deep neural networks (DNNs) in embedded micro-processor systems. A DRP unit (supporting 16b FP from this generation) and a newly designed multiply-and-accumulate (MAC) unit are tightly integrated into an STP...

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Bibliographic Details
Published in2018 IEEE Symposium on VLSI Circuits pp. 41 - 42
Main Authors Fujii, Taro, Toi, Takao, Tanaka, Teruhito, Togawa, Katsumi, Kitaoka, Toshiro, Nishino, Kengo, Nakamura, Noritsugu, Nakahara, Hiroki, Motomura, Masato
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.06.2018
Subjects
Acceleration
Computer architecture
Convolution
Engines
Kernel
Micromechanical devices
System-on-chip
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Summary:We have developed 3rd generation DRP, dynamically reconfigurable processor, for accelerating deep neural networks (DNNs) in embedded micro-processor systems. A DRP unit (supporting 16b FP from this generation) and a newly designed multiply-and-accumulate (MAC) unit are tightly integrated into an STP-3 AI core to achieve high versatility, high performance, and low latency DNN processing. The core also features narrow bit-width streaming data exchange mechanism between the two units. Not only basic 16b FP but also binarized DNN inference computations are supported.
DOI:10.1109/VLSIC.2018.8502438