A distributed current stimulator ASIC for high density neural stimulation

This paper presents a novel distributed neural stimulator scheme. Instead of a single stimulator ASIC in the package, multiple ASICs are embedded at each electrode site for stimulation with a high density electrode array. This distributed architecture enables the simplification of wiring between ele...

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Bibliographic Details
Published in2016 38th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC) Vol. 2016; pp. 1770 - 1773
Main Authors Jeong Hoan Park, Chaebin Kim, Seung-Hee Ahn, Tae Mok Gwon, Joonsoo Jeong, Sang Beom Jun, Sung June Kim
Format Conference Proceeding Journal Article
LanguageEnglish
Published United States IEEE 01.08.2016
Subjects
Cochlear implants
Current measurement
Electric Stimulation
Electrodes
Equipment Design
Generators
Metals
Prosthetics
Voltage measurement
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Summary:This paper presents a novel distributed neural stimulator scheme. Instead of a single stimulator ASIC in the package, multiple ASICs are embedded at each electrode site for stimulation with a high density electrode array. This distributed architecture enables the simplification of wiring between electrodes and stimulator ASIC that otherwise could become too complex as the number of electrode increases. The individual ASIC chip is designed to have a shared data bus that independently controls multiple stimulating channels. Therefore, the number of metal lines is determined by the distributed ASICs, not by the channel number. The function of current steering is also implemented within each ASIC in order to increase the effective number of channels via pseudo channel stimulation. Therefore, the chip area can be used more efficiently. The designed chip was fabricated with area of 0.3 mm 2 using 0.18 μm BCDMOS process, and the bench-top test was also conducted to validate chip performance.
ISSN:1557-170X
DOI:10.1109/EMBC.2016.7591060