Coherent interconnect/substrate modeling using SPACE - an experimental study

The functionality of modern ICs increasingly suffers from substrate noise. Digital transistors switching at high frequencies are known to induce substrate noise through their bulk contacts. In addition, interconnects carrying aggressive, high-frequency signals are known to induce substrate noise thr...

Full description

Saved in:
Bibliographic Details
Published inESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003 pp. 585 - 588
Main Authors Schrik, E., van Genderen, A., van der Meijs, N.P.
Format Conference Proceeding
LanguageEnglish
Published IEEE 2003
Subjects
Circuit noise
Circuit simulation
Clocks
Coupling circuits
Frequency
Integrated circuit interconnections
Integrated circuit noise
Noise level
Packaging
Space technology
Online AccessGet full text

Cover

More Information
Summary:The functionality of modern ICs increasingly suffers from substrate noise. Digital transistors switching at high frequencies are known to induce substrate noise through their bulk contacts. In addition, interconnects carrying aggressive, high-frequency signals are known to induce substrate noise through their capacitive coupling with the substrate. In this paper, we describe how our layout-to-circuit extractor SPACE builds a coherent interconnect/substrate model from a layout. The result is a comprehensive circuit model which can immediately be simulated by a regular circuit simulator. We evaluate our modeling approach by extracting a ring-oscillator layout and simulating the resulting circuit with HSPICE. We have done extractions, under varying conditions; the simulation results give practical insight into relevant substrate noise phenomena.
ISBN:0780379993
9780780379992
DOI:10.1109/ESSDERC.2003.1256944