Design of 8-bit SAR-ADC CMOS
Successive approximation analog-to-digital converter (ADC) implemented in a conventional 0.18¿m CMOS technology with low voltage. The SAR composite of sample-and-hold dummy switch compensation was employed, comparator is low-voltage latched and realized based on current-mode approach, control logic...
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Published in | 2009 IEEE Student Conference on Research and Development (SCOReD) pp. 272 - 275 |
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Main Authors | , , , |
Format | Conference Proceeding |
Language | English |
Published |
IEEE
01.11.2009
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Subjects | |
Online Access | Get full text |
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Summary: | Successive approximation analog-to-digital converter (ADC) implemented in a conventional 0.18¿m CMOS technology with low voltage. The SAR composite of sample-and-hold dummy switch compensation was employed, comparator is low-voltage latched and realized based on current-mode approach, control logic circuit and digital-to-analog conversion consists of binary weighted capacitor arrays for the differential inputs. The ADC has INL and DNL of 0.45 LSB for supply voltage 1.8V, at sampling rate 200 KS/S and signal to noise ratio distortion is 58.5 dB. This design is suitable for standard CMOS technology with low-power low-cost VLSI implementation. It is well applied when embedded into system-on-chip (SOC) circuit designs. |
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ISBN: | 9781424451869 1424451868 |
DOI: | 10.1109/SCORED.2009.5443038 |