Multiplexed oversampling digitizer in 65 nm CMOS for column-parallel CCD readout

• Published in: 2011 IEEE Nuclear Science Symposium Conference Record pp. 1435 - 1440
• Main Authors: Grace, C. R., Walder, J-P, von der Lippe, H.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.10.2011
• Subjects: Application specific integrated circuits; Clocks; CMOS integrated circuits; Field programmable gate arrays; Generators; Multiplexing
• ISBN: 1467301183; 9781467301183
• ISSN: 1082-3654; 2577-0829
• DOI: 10.1109/NSSMIC.2011.6154344

A digitizer designed to read out column-parallel charge-coupled devices (CCDs) used for high-speed X-ray imaging is presented. The digitizer is included as part of the High-Speed Image Preprocessor with Oversampling (HIPPO) integrated circuit. The digitizer module comprises a multiplexed, oversampling, 12-bit, 80 MS/s pipelined Analog-to-Digital Converter (ADC) and a bank of four fast-settling sample-and-hold amplifiers to instrument four analog channels. The ADC multiplexes and oversamples to reduce its area to allow integration that is pitch-matched to the columns of the CCD. Novel design techniques are used to enable oversampling and multiplexing with a reduced power penalty. The ADC exhibits 188 μV-rms noise which is less than 1 LSB at a 12-bit level. The prototype is implemented in a commercially available 65 nm CMOS process. The digitizer will lead to a proof-of-principle 2D 10 Gigapixel/s X-ray detector.