Minimum energy CMOS design with dual subthreshold supply and multiple logic-level gates
This paper presents a method for minimum energy digital CMOS circuit design using dual subthresh-old supply voltages. Stringent energy budget and moderate speed requirements of some ultra low power systems may not be best satisfied just by scaling a single supply voltage. Optimized circuits with dua...
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Published in | 2011 12th International Symposium on Quality Electronic Design pp. 1 - 6 |
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Main Authors | , |
Format | Conference Proceeding |
Language | English |
Published |
IEEE
01.03.2011
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Subjects | |
Online Access | Get full text |
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Summary: | This paper presents a method for minimum energy digital CMOS circuit design using dual subthresh-old supply voltages. Stringent energy budget and moderate speed requirements of some ultra low power systems may not be best satisfied just by scaling a single supply voltage. Optimized circuits with dual supply voltages provide an opportunity to resolve these demands. The delay penalty of a traditional level converter is unacceptably high when the voltages are in the subthreshold range. In the present work level converters are not used and special multiple logic-level gates are used only when, after accounting for their cost, they offer advantage. Starting from a lowest per cycle energy design whose single supply voltage is in the subthreshold range, a new mixed integer linear program (MILP) finds a second lower supply voltage optimally assigned to gates with time slack. The MILP accounts for the energy and delay characteristics of logic gates interfacing two different signal levels. New types of linearized AND and OR constraints are used in this MILP. We show energy saving up to 24.5% over the best available designs of ISCAS'85 benchmark circuits. |
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ISBN: | 9781612849133 161284913X |
ISSN: | 1948-3287 1948-3295 |
DOI: | 10.1109/ISQED.2011.5770804 |